[Slide 1 L1.2] Welcome back to Unit 1.
We learned a little bit about transistors
in the previous lecture.
But to really appreciate what transistors are for
and what I-V characteristics we are looking for
in a transistor, we need to understand something about
the circuits that they're used in.
This lecture is about digital circuits.
The next lecture is about analog circuits.
So it's going to be a very quick look at some of the
key considerations in digital circuits.
[Slide 2] So in a digital circuit, we're going to think about
the transistor as a switch.
It's either opened or closed
and that'll represent a 1 or a 0.
[Slide 3] Recall from the last lecture that there are two flavors
of transistors in CMOS, complementary technology.
There's an n-channel device
where the electrons carry the current.
And for the n-channel device,
the transistor switch is closed.
Current flows when the voltage we apply
between the gate and the source is more positive
than a critical voltage called a threshold voltage.
[Slide 4] The complementary device is a p-channel MOSFET.
We indicate it here with an open circle on the gate,
so that we can keep them straight.
In a p-channel MOSFET, the current is carried by holes,
positive charge carriers.
In order to close the switch and allow current to flow,
we need to apply a voltage between the gate and the source
that is more negative than the threshold voltage.
And the threshold voltage will be a negative number.
[Slide 5] So we have both flavors of transistors
and we use both of those transistors
in the basic building block for a CMOS digital circuits.
And the basic circuit is what we call a CMOS inverter.
It has an n-channel transistor on the bottom
and it has a p-channel transistor on the top.
The n-channel transistor is connected,
so that its source is grounded.
The gates of both transistors are connected together.
And the drain of the n-channel transistor is
connected to the output.
Now, the p-channel transistor is actually upside down.
In the p-channel transistor,
the drain is connected to the output.
The gate is connected with the other gate
together in the input.
And the source is connected to the most positive
power supply voltage in the circuit.
So this is our basic circuit that we're using
in digital electronics.
There's an input to the gates.
There's an output voltage taken from the two drains.
[Slide 6] Now, to understand how this circuit operates,
we just think of the transistors as switches.
They're either open or closed.
So let's think about applying a large positive voltage,
more positive than the threshold voltage of the n-channel.
That large voltage is going to represent the digital 1.
That voltage will be enough to turn on the NMOS transistor
and connect this switch to ground.
But it will not be enough.
The large voltage here, 1, and the large voltage
on the source means there's no voltage difference
between the gate and the source of the PMOS.
That switch is open.
The output is connected to ground,
so the output voltage is low.
And input 1 has been converted to an output 0.
The device functions as an inverter.
It inverted a 1 to a 0.
Now, I'll point out that in an ideal transistor,
there would be zero current flow.
But in real transistors, there'll be some leakage current.
Even though one of the switches is open,
there's a little bit of leakage current that can flow
and that leakage current is becoming important these days,
has become very important.
[Slide 7] Now we can also look at applying a low voltage to the input.
That would be a logic 0.
The low voltage wouldn't be enough
to turn on the NMOS device, so that switch is open.
But if I look at the low voltage on the gate
and the high voltage on the source of the PMOS,
that's a very large negative voltage
between the gate and the source of the PMOS.
That turns on the PMOS, that connects the output
to the large positive power supply voltage
and we have an output 1.
So again, the circuit inverts
and input 0
to a output 1.
So that's the basic function of the CMOS inverter.
The beauty of this device is that in principle,
no current flows,
only during transients while we're switching from 1 to 0.
In practice, there'll be a little bit of leakage current
that will flow because one of the two transistors
is always open-circuited.
[Slide 8] So we can build logic gates in the CMOS circuits
from this basic CMOS inverter concept.
You may recall one of things you learned
when you take a first course in boolean logic is an AND.
The AND function, both of the inputs need to be 1
for in order for the output to be 1.
Turns out it's easier because we're thinking about
building circuits with inverters to implement a not AND
or a NAND gate.
So a NAND gate would have a
1 on the input, only when both--
or a 0 on the zero, only when both inputs are 1.
To understand how this device functions,
simply pick one of the cases.
Here we have a 1 on input A, a 0 on input B,
and we'll have a 1 on the output.
Just trace through this circuit,
convince yourself that there is only one and only one path
to a switch that is closed
to either the positive power supply or the ground,
and we'll get either a 1 or a 0
in each of the cases out of that.
So convince yourself that this truth table is true.
This is a basic digital gate built out of CMOS inverters.
[Slide 9] Now, if we back to the basic CMOS inverter,
we can ask what is its transfer characteristic.
The transfer characteristic is the output voltage
as we sweep the input voltage.
In the ideal CMOS inverter where we're just opening
and closing switches, the output voltage would be high
until the input voltage is big enough to flip
the n-channel switch and connect the output
to ground or 0 voltage.
So we'd have a transistor characteristic that would look,
or an inverter characteristic that would look like this.
In practice, the real devices will show some hopefully
sharp transition between high voltage and low voltage.
And we hope that we have I-V characteristic,
or a transfer characteristic that looks something like this.
Now, one of the very important features of this circuit
is that there's a significant range of voltages
here at the low end.
Doesn't matter precisely what the small input voltage is.
Doesn't have to be exactly 0.
As long as it's small enough, we'll get exactly VDD
or logic 1 out.
Same thing on the high end.
We have a noise margin there.
It doesn't matter precisely how large the high voltage is.
As long as it's large enough, we'll get exactly
the low voltage logic 0 out that we're looking for.
These noise margins are very important.
When we're building complicated circuits,
errors would add up.
But what these noise margins do is they continually reset
the logic values to their appropriate values and
large-scale integration, large-scale circuits
would not be possible without noise margins.
Now, another feature of this transfer characteristic
is its steepness.
If we were to look right in the middle
of that transfer characteristic
and ask what's the slope there,
the slope is the voltage gain.
The slope is basically the change in output voltage
for a change in input voltage.
So the magnitude of that is very large
if this transition is very steep.
[Slide 10] Now, voltage gain is important in analog circuits.
But voltage gain is also important in digital circuits
because voltage gain does something very important for us.
Consider, for example, if the magnitude of the voltage gain
was 1, we would just have this straight line
with a slope of negative 1 there.
You can see that our noise margins have disappeared.
We would have no tolerance to noise and errors.
It would not be possible to produce large-scale
digital circuits without the errors accumulating
and destroying the operation.
So a fundamental consideration is that a transistor
or any device we're going to use for digital logic
should have gain in order to provide noise margins
that make these circuits possible.
[Slide 11] So this is our basic CMOS inverter.
It consists of two transistors.
The PMOS on top is often called the pull-up transistor
because its function, when the switch is closed,
is to pull the output voltage
up to the power supply voltage.
The n-channel transistor is often called
the pull-down transistor.
Its function, when closed, is to pull the output voltage
down to the ground, 0 voltage.
Very little current flows in this circuit
unless we're actually doing the switching transient itself.
That's a beautiful feature of this circuit.
Good noise margins occur when we have voltage gain.
So it's important that we have gain.
But the next two questions that we have is about
how fast can we operate this circuit
and how much power do we dissipate
while we're operating this circuit.
Those are very important questions for the design
of large-scale integrated circuits.
[Slide 12] So let's think about what happens as we switch
from a 0 to a 1.
So if we look at a 1 to a 0 transition on a gate,
when we switch low, that will open the n-channel device,
and that will close the p-channel device.
Since the p-channel device is closed,
we have a direct connection to the power supply,
current flows down, and charges this capacitor.
This capacitor, I've labeled C sub SW.
We call it the switching capacitance.
It represents all of the connections of the wire
from the output node to all of the other gates
that are being driven and all of the wires
that are connected to it,
to get the signals around the circuit.
So during this 1 to 0 transition,
we charge up all of those capacitors
to the power supply voltage.
So after that transition is made,
we're now have a high voltage stored on the capacitor.
The NMOS is open.
The only current that flows now
is this small leakage current.
[Slide 13] If we look the other direction,
if we switch from a logic 0 to a logic 1,
well, the high logic 1 will close the n-channel transistor.
It will open the p-channel transistor.
We now have a connection from the capacitor to ground.
The capacitor can discharge with a current ION flowing,
discharging the capacitor.
That will take the high voltage,
bring it back down to a low voltage,
and then we're left in a logic 0
when that transient is all over.
When the transient is all over, the only currents
that are flowing are these small leakage currents
because we have two transistors in series,
one of them is open.
Okay, so the next question we have is
how fast, how quickly can we charge
and discharge this capacitor?
That determines the speed of the circuit,
the speed of our microprocessor
or whatever it is that we're building.
[Slide 14] Well, let's just look at the discharge cycle
because things are symmetric.
And if we do the discharge cycle,
we basically have the whole story.
So let's think about the n-channel.
The capacitor has been charged up
to the power supply voltage.
We switch from low to high.
That closes the switch.
The NMOS device is on.
Current flows through the n-channel transistor.
There will initially be a large voltage across the terminal,
so the transistor is in the saturated region.
A large current will flow out of the capacitor into ground
and will discharge that capacitor.
So the question we have is, how long does it take
to discharge that capacitor?
Well, the charge that was stored, we remember
from our basic electrical engineering course
that the charge on a capacitor is capacitance times voltage,
so we know what the charge was initially
that was stored there.
We also know that the definition of current
is charge divided by time.
So these two relations we can solve and find the time
it takes to pull the charge out of that capacitor.
It's just C, the switching capacitance,
times the power supply voltage,
divided by the on-current that flows through the transistor.
Okay, so that's a very important relation
because it tells us what controls the speed of the circuit.
The speed depends on the DC on-current that flows
through the transistor.
And the same thing happens during the charging cycle.
When the capacitor is charging,
it will charge through the PMOS.
And the speed of the charging process will depend on
the on-current of the PMOS.
[Slide 15] Now, I'll just mention,
although I won't very much about this,
there are also speed considerations with all of the wires
that are used to connect up the various transistors
and gates in an integrated circuit chip.
And there's an awful lot of wires in today's chips
because there's an awful large number of gates
that need to be connected.
Years ago, the transistor speed itself determined
the speed of the circuit.
But we're at a situation now where the speeds,
due to all of these wires and these interconnects,
is really a dominant consideration.
And designers work very hard to manage these speeds
such that the overall performance of the circuit
is more controlled by the transistor
than by the wires themselves.
[Slide 16] Okay, we've understood speed.
We also have to understand power dissipation
because we'll usually have a power budget.
We want the batteries in our portable electronic devices
to last a long time.
If we have a large server farm,
we don't want to consume too much power.
So we have to be concerned about the power
that's being consumed while we're operating this circuit.
So we understand the switching speed,
but there are two different aspects to the power.
There's a dynamic power that is consumed
while we're doing the switching
and while the micro-processor is doing its work.
But there's also a static power.
When the CMOS gate is just sitting there, not switching,
either a 1 or a 0 on its input,
ideally, there would be no power dissipation at all.
In practice, there's some leakage current
and that has become quite important,
important enough for us to discuss.
But let's talk about dynamic power first.
[Slide 17] So let's consider that we have an input signal
that is switching rapidly between 0 and 1
at some frequency F.
So period, capital T.
When we apply that,
during the times when the input signal is low,
the NMOS is open-circuited, the PMOS is turned on,
current flows from the power supply through the PMOS,
charges the transistor up.
Charges it up and you may recall that the energy stored
in the capacitor after you've charged it up
is one-half capacitance times voltage squared.
Okay, so after the charging sequence,
we've stored energy in the capacitor.
When the signal then goes high in the next phase,
we turn the n-channel transistor on,
we turn the p-channel transistor off.
All of that energy we've stored in the capacitor
is now dumped to ground through the n-channel transistor.
That's where the power dissipation is occurring.
So let's look at that.
[Slide 18] Let's just look at the discharge cycle.
You can actually show that the same amount of power
is dissipated on the charging cycle.
So on a discharge cycle, we have capacitor that's charged up
and we are discharging it through the transistor to ground.
And we're asking, you know,
what's the power associated with that?
So all of that will take place during the half period
when the signal on the gate is high.
Well, initially, we stored an energy one-half CV-squared
on the capacitor.
At the end of this transient, there'll be no energy left.
All of that energy has been dissipated.
Power is the energy dissipated, divided by the time it took
to dissipate it.
You know, power is joules per second.
Joules of energy stored,
the seconds that it took for us to discharge the capacitor.
We just put in the one-half CV-squared, energy stored,
the half-period T over two,
and we find that the power is frequency times capacitance
times voltage squared.
The faster we run the circuit, the more power it consumes,
the more capacitance, the more power.
The higher the voltage is, the more power that's consumed.
So this is our dynamic power.
And the factor alpha here is something we've introduced
called an activity factor.
It represents the fraction of the time
that this particular gate is switching.
Not all gates switch every cycle.
This might be a few percent.
[Slide 19] Okay, so we've done the dynamic power.
We've discussed the dynamic power.
And we see that at a given frequency,
the dynamic power is proportional
to the power supply voltage squared
and to the frequency.
So we can't run the chip too fast
or it will dissipate too much power.
And there's a lot of motivation for looking for transistors
that operate at low voltages.
Okay, that's the dynamic power.
[Slide 20] But the non-ideal CMOS gate also dissipates some power
when it's not switching.
That power comes from the leakage current.
If we either have a 0 or a 1 on the input,
one of the two transistors is open-circuited,
but some leakage current flows.
As transistors have gotten smaller and smaller
over the years, these leakage currents have increased.
They're still small, but when we have
billions of transistors on a chip, they can add up.
The power dissipation, then,
we just have a leakage current, I-off,
that's the current flowing when the transistor is off,
times the power supply voltage.
If there are a large number of gates,
then that static power dissipation can add up
and be significant.
[Slide 21] So here are our basic considerations
about CMOS speed and power.
First of all, the speed is determined by on-current.
The higher the current that the transistor delivers,
the faster we can charge and discharge the capacitors.
So on-current is important for speed.
The faster we operate the circuit,
the more power we dissipate.
So this has led, in the last several years,
to a limitation on how fast we can run micro-processors.
We simply consume too much power if we run them any faster.
Lower power supply voltage means lower power,
especially dynamic power goes as voltage squared.
So there's a lot of incentive to use transistors
that operate at as low a voltage as possible.
And finally, leakage is bad.
The more leakage we have,
the more static power dissipation we have
and that's not good.
[Slide 22] So we're at an area now where
most electronics design is power constrained.
You'll be given a power budget.
You know, maybe if you're designing a chip
for a laptop computer, you might be permitted to dissipate
100 watts per centimeter squared.
If you're designing a product that's intended to
send signals and send information back to a central computer
and has to live for a long time
without running down a battery,
the power dissipation might be a lot less.
So there is some power dissipation limit that we begin with.
Now, if I look at power versus integration density,
the more complex my circuit, the more transistors on a chip,
the more leakage current is going to add up
and I'll have more static power dissipation.
If I went to an extreme and put too many transistors
on a chip, I would consume my entire power budget
with leakage power and not be able to do anything useful.
The useful work is done when I'm switching the gates.
That's the dynamic power.
If I have only a small level of integration density,
a small number of transistors on the chip,
all of my power can be dynamic power,
doing some useful computation or whatever.
But as I put larger and larger numbers of transistors
on the chip and make the chip more and more complex,
I'll have more leakage current
and I have to make sure that
the sum of the static power
and the dynamic power add up to my power budget
that I have to live within.
So this has really become a serious issue
in the last decade or so.
And it really limits the speed with which we can operate
digital circuits without exceeding power budgets.
[Slide 23] So we've talked about a lot of things,
but there are really only a few major points
that you need to understand about digital circuits
in order to appreciate
how transistors affect the performance of digital circuits.
So we build digital circuits with complementary devices,
both n-channel and p-channel devices.
The basic building block is the CMOS inverter,
which has some wonderful characteristics.
One of the things that we require from transistors
and from their circuit is that we have voltage gain
because voltage gain provides us with noise margins,
which are critical for doing digital computation
with large numbers of gates so that errors don't accumulate.
And then we've seen how on-current, off-current,
and power supply voltage are critical parameters.
They control speed and power
and they have a very important impact on
any circuit that we implement and design
with CMOS technology.
[Slide 24] Okay, so we've learned a little bit about digital circuits,
enough for this course.
We want to learn just a little bit about analog circuits,
so we can appreciate how the characteristics of transistors
affect the analog performance of circuits.
And that will be the topic of the next lecture.

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